FIG. 1 shows a conventional high-speed differential analog circuit 10. Differential circuit 10 includes differential input terminals Rx+ and Rx−, input buffer 12, termination resistors 14 and 16, common mode resistor 18, and conventional common mode voltage source 20. Differential input terminals Rx+ and Rx− are configured to receive a single differential input signal. Termination resistors 14 and 16 typically have the same resistance. Common mode voltage source 20 provides a common mode voltage VCOMMON to common mode resistor 18. The operation of this conventional circuit is well-known.
Input buffers, including differential analog input buffers such as input buffer 12, typically require some kind of protection against overvoltages that may be inadvertently applied to a terminal thereof. For example, both externally-applied DC and alternating current (AC) power sources are configured to provide a nominal power supply, or standard voltage, to an integrated circuit (IC) for its operation. On occasion, these power sources may pass transient or sustained voltages significantly above nominal to the IC. In addition, human handlers and/or electronic equipment may carry or generate a significant static electrical charge, sometimes on the order of a thousand to two thousand volts or more. For example, when such a human handler inadvertently touches the leads of an IC and passes such a high static charge to an input buffer on the IC, significant (and sometimes fatal) damage can be done to the IC if the IC is without some kind of protection against such overvoltages.
FIG. 2 shows a conventional high-speed differential analog circuit 50, further equipped with conventional overvoltage protection devices 52 and 54. Differential analog circuit 50 is structurally the same as differential analog circuit 10 of FIG. 1, but with the addition of overvoltage protection devices 52 and 54 to differential input nodes 56 and 58. Overvoltage protection devices 52 and 54 generally provide a low-energy conductance path for overvoltages that are inadvertently applied to the input buffer terminals or leads Rx+ and Rx− to be safely carried to a ground potential, away from the overvoltage-sensitive transistors and other circuitry that may make up the input buffer 12. The operation, structure and design of conventional overvoltage protection devices 52 and 54 are also quite well-known.
However, overvoltage protection devices 52 and 54 are electrically connected to input nodes 56 and 58. As a result, the RC time constant associated with input nodes 56 and 58 is higher than the corresponding RC time constant associated with input nodes 26 and 28 of the circuit 10 of FIG. 1. As a result, the high-speed performance and capabilities of circuit 50 and any IC including it are slightly degraded, relative to circuit 10. Furthermore, overvoltage protection devices 52 and 54 are generally in relatively close physical proximity to input nodes 56 and 58, creating additional parasitic capacitances that do not affect input nodes 26 and 28 of the circuit 10 of FIG. 1. These additional parasitic capacitances further degrade the high-speed performance and capabilities of circuit 50, relative to circuit 10.
As signal transmission speeds increase, a need exists to retain or preserve maximum speed and performance of differential analog input circuitry. However, as IC operating voltages and transistor sizes decrease, the need to protect overvoltage-sensitive devices on an IC is felt even more strongly felt.